Improvements in semiconductor processing technologies and design tools have allowed for more and more functions to be integrated together on a single integrated circuit (IC) chip. Such improvements allowed for cache memories to be integrated onto the same chip as a central processing unit (CPU) core. More recently, multiple CPU cores are being integrated onto the same chip along with one or more memories.
As this trend continues, multiple CPU cores and multiple memory blocks will be integrated together. FIG. 1 shows a multi-processor system chip. Processor cores 10, 10′, 10″ are integrated together onto IC chip 20. Each processor core may execute a separate stream of instructions and each accesses its own local cache memory, caches 12, 12′, 12″. When data is not found in the local cache memory (a cache miss), memory controllers 14, 14′, 14″ fetch the desired data from an external memory, such as using an external bus to a large external main memory.
Snoop tags 16 contain directory information about the entries currently being stored in caches 12, 12′, 12″. Cache coherency is achieved through the use of snoop tags 16, perhaps in conjunction with external directories and other controllers.
The higher integration of functions onto a single silicon die is primarily achieved by using a higher density of transistors. Transistors generate heat as a by-product as do resistances. Transistors operating at a very high frequency may get too hot, even causing some localized melting or other damage, reducing long term reliability. Such heat is drawn away through a package containing the IC chip, but the amount of heat dissipated is limited.
Power management of highly integrated systems is critical to prevent such damage. Power management unit 18 may be included on IC chip 20. Power management unit 18 may be activated by a sensor such as a temperature detector or by a software monitor or program to reduce power consumption on IC chip 20. For example, power management unit 18 may cause processor cores 10, 10′, 10″ to enter a lower-power state when the sensed temperature is above a limit. The low-power state may be a reduced frequency of operation or periodically halting operation to allow IC chip 20 to cool.
A wide variety of lower-power modes and power management units and techniques are known. However, most are relatively simple and are designed for use with simple systems, such as single-processor chips. While such single-processor power-management techniques could simply be replicated for each of the multiple CPU's on a multi-processor chip, the power management achieved would be disjointed and lack coordination among the many processor-memory clusters sharing the same IC chip die.
What is desired is power management for a more complex multi-processor chip. A power management system that can control multiple CPU cores and multiple memory blocks that can operate independently of one another is desirable. Centrally-coordinated power management of multiple processor-memory clusters is desirable.